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| ASIC Designer / VLSI Design Engineer
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| Looking for a job in VLSI.
Skills: Verilog,VHDL,C,XML,HTML,JAVA
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| Resume reference: | enyqRxBb | |
| Date last updated: | June 19, 2008 | |
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| Education: | Bachelor's degree - Electronics and communication | |
| Experience: | 1 year | |
| Employment situation: | Studying | |
| Salary expectations: | 70K | |
| Availability: | Immediately | |
| Type of employment: | Full Time, Part Time, Traineeship | |
| Location: | CA/San Jose - Santa Clara | |
| Looking to work in: | CA/San Francisco, CA/San Jose, IL/Chicago | |
| Age: | 24 | |
| Gender: | Male | |
| Marital status: | Single | |
| Own transport: | Yes | |
| Driver's license: | Yes | |
| Citizenship: | Indian | |
| Right to work | Yes, I have residence/work permit | |
| English level: | Fluent | |
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